Power Aware Verification

Active power management

Power reduction techniques

Power management concepts

Power management architecture

Unified Power Format

Power Aware Design and Verification Flow

Elements of Low Power Verification Methodology

Some elements required by almost all designs are:

• Use of voltage aware booleans for logic behavior
• Use of voltage aware models for mixed signals components
• Testing of reset and retention functions
• Power aware assertions
• Power management coverage
• Random asynchronous stimulus generation to exercise the concurrent power management events
• Adoption of firmware validation approach to exercise true in-system functionality of the device

– VMM LP